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PRELIMINARY
CYM1846V33
512K x 32 3.3V Static RAM Module
Features
* High-density 3.3V 16-megabit SRAM module * 32-bit Standard Footprint supports densities from
16K x 32 through 2M x 32
* High-speed SRAMs
module is constructed from four 512K x 8 SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. The CYM1846V33 is designed for use with standard 72-pin SIMM sockets. The pinout is downward compatible with the 64-pin JEDEC ZIP/SIMM module family (CYM1821, CYM1831, CYM1836, and CYM1841). Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 1,024K words (CYM1851). The CYM1846V33 is offered in vertical SIMM configuration and is available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. Presence detect pins (PD 0-PD3) are used to identify module memory density in applications where modules with alternate word depths can be interchanged.
-- Access time of 12 ns
* Low active power
-- 1.650W (max.) at 12 ns
* 72 pins * Available in ZIP, SIMM format
Functional Description
The CYM1846V33 is a high-performance 3.3V 16-megabit static RAM module organized as 512K words by 32 bits. This
Logic Block Diagram
PD0 PD1 PD2 PD3 OPEN OPEN GND OPEN
Pin Configuration
ZIP/SIMM Top View
A0-A18
OE WE
19
512K x 8 SRAM CS1 512K x 8 SRAM CS2 512K x 8 SRAM CS3 512K x 8 SRAM CS4
8
I/O0-I/O7
I/O7-I/O15
8
8
I/O16-I/O23
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND NC NC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS 4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC
1846V33-2
8
I/O24-I/O31
1846V33-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 May 3, 1999
PRELIMINARY
Selection Guide
1846V33-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Shaded area contains advanced information.
CYM1846V33
1846V33-15 15 800 120
1846V33-20 20 780 120
1846V33-25 25 780 120
1846V33-35 35 780 120
12 820 120
Maximum Ratings [1]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied ............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ................................................ -0.5V to +VCC
DC Input Voltage ............................................-0.5V to +4.6V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V + 10% / -5%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < V I < V CC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CSN < VIL, F = F MAX -12 -15 -20,-25,-35 ISB1 Automatic CS Power-Down Current[2] Max. VCC, CS > VIH, Min. Duty Cycle = 100% -12 -15 -20,-25,-35 ISB2 Automatic CS Power-Down Current[2] Max. VCC, CS > VCC - 0.2V, V IN > VCC - 0.2V, or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.0 -0.3 -10 -10 Min. 2.4 0.4 VCC + 0.3 0.8 +10 +10 820 800 780 180 160 140 120 Max. Unit V V V V A A mA mA mA mA mA mA mA
Shaded area contains advanced information.
Capacitance[3]
Parameter CINA CINB COUT Description Input Capacitance (WE, OE, A 0-18) Input Capacitance (CS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 32 8 8 Unit pF pF pF
Notes: 1. If device is operated at these settings, long term reliability will be affected. 2. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 3. Tested on a sample basis.
2
PRELIMINARY
AC Test Loads and Waveforms
R1 315 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 351 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 351 R1 315 3.0V 90% GND 5 ns 10%
CYM1846V33
ALL INPUT PULSES 90% 10% 5 ns
(a)
1846v33-3
(b)
1846v33-4
(c)
1846v33-5
Equivalent to: OUTPUT
THEVENIN 167
EQUIVALENT 1.73V
Switching Characteristics Over the Operating Range[4]
1846V33-12 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD WRITE CYCLE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[7]
1846V33-15 Min. 15 Max. Unit ns 15 3 15 8 0 8 3 8 15 15 10 10 0 1 12 8 1 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z
[5] [5, 6]
Min. 12
Max.
12 3 12 7 0 7 3 7 12 12 9 9 0 1 10 7 1 3 0 7
CS HIGH to High Z
CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[6]
0
Shaded area contains advanced information. Notes: 4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 6. t HZCS and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
PRELIMINARY
Switching Characteristics Over the Operating Range[4] (continued)
1846V33-20 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z
[5] [5, 6]
CYM1846V33
1846V33-25 Min. 25 Max.
1846V33-35 Min. 35 Max. Unit ns 35 3 35 18 0 15 3 15 35 35 30 30 3 2 30 20 2 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
Description
Min. 20
Max.
20 3 20 12 0 10 3 10 20 20 17 17 3 2 15 12 2 3 0 12 25 20 20 3 2 20 15 2 3 0 3 0 3
25 25 15 12 12 25
CS HIGH to High Z
CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[6]
WRITE CYCLE[7]
12
0
Switching Waveforms
Read Cycle No. 1[8, 9]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1846V33-6
Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CS = VIL, and OE= VIL.
4
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 [8,10]
tRC CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU V CC SUPPLY CURRENT 50% DATA VALID tHZOE tHZCS
CYM1846V33
HIGH IMPEDANCE
tPD ICC 50% ISB
1846V33-7
Write Cycle No. 1 (WE Controlled)
[7]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1846V33-8
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Note: 10. Address valid prior to or coincident with CS transition LOW.
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled)
[7,11]
CYM1846V33
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1846V33-9
tSCS
tHA
tHD
Truth Table
CS H L L L WE X H L H OE X L X H High Z Data Out Data In High Z Inputs/Output Deselect/Power-Down Read Write Deselect Mode
Ordering Information
Speed (ns) 12 Ordering Code CYM1846V33PM-12C CYM1846V33P8-12C CYM1846V33PZ-12C 15 CYM1846V33PM-15C CYM1846V33P8-15C CYM1846V33PZ-15C 20 CYM1846V33PM-20C CYM1846V33P8-20C CYM1846V33PZ-20C 25 CYM1846V33PM-25C CYM1846V33P8-25C CYM1846V33PZ-25C Package Type PM21 PM21 PZ11 PM21 PM11 PZ11 PM21 PM21 PZ11 PM21 PM21 PZ11 Package Type 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module Operating Range Commercial
Shaded area contains advanced information. Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
6
PRELIMINARY
Ordering Information (continued)
Speed (ns) 35 Ordering Code CYM1846V33PM-35C CYM1846V33P8-35C CYM1846V33PZ-35C Document #: 38-M-00089-A Package Type PM21 PM21 PZ11 Package Type 72-Pin Plastic SIMM Module
CYM1846V33
Operating Range Commercial
72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module
Package Diagrams
72-Pin Plastic SIMM Module PM21
72-Pin Plastic ZIP Module PZ11
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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